Designing and fabricating integrated circuit devices typically involves many steps, sometimes referred to as the “design flow.” Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. Many of these steps are extremely time consuming, taking up to several days for just one simulation, and a circuit layout design will make many iterations through each of the different phases, passing back further up in the flow to try again after a problem is discovered. Pattern matching provides approximate, but fast evaluation of sensitivities of a layout to lithographic effects and helps reduce the number of iterations through the flow.
Some pattern matching methods are DRC (Design Rule Checking)-based. In a DRC-based pattern matching process, a pattern to be searched (search pattern) is converted into a set of DRC rules first, the layout design is then checked using the set of DRC rules, and finally the output is analyzed to obtain pattern matches. While faster and more accurate than other approaches, existing DRC-based methods tend to generate a large number of complex DRC rules. The complex DRC rules not only are difficult for users to understand but can also cause high computation costs. Moreover, fuzzy pattern matching or partial pattern matching is difficult to implement using the complex DRC rules. It is thus desirable to develop a new DRC-based method that can address these shortcomings.